The present invention generally relates to a method for operating non-volatile memory, and more particularly, to a method for operating non-volatile memory with a symmetrical dual-channels.
With the rapid developments of electronic industry and computer technology, the electronic products are widely used in daily routines and improve the quality of the life. Generally, a variety of memories are utilized in many electronic products to provide temporary space for switching and storing data. On the one hand, the nonvolatile characteristic of the flash memory allows repeated writing to record the data status, but the flash memory does not need a power supply and periodic refreshing. On the other hand, due to improvements in the flash memory""s structure and semiconductor techniques, the flash memory can accumulate a great number of cells since the dimensions of the integrated circuits (ICs) are greatly reduced.
The size reduction of the device may also shrink the data signal, with the result that the reading speed decreases the overall performance of the flash memory. Even charges stored in the cell are lost such that the cell""s life is reduced when a higher drain voltage is employed. More severely, the reading speed of data signals is read in proportion to the reading current through the memory cell, so the reading speed may be slower due to the minimized reading current.
Conventionally, for the same channel length of memory cell, even a small increase in the channel length to enhance the reading current greatly increases the circuit size, resulting in the increment of the IC""s integrity. FIGS. 1A-1B show a local view and the cross-sectional views along the Axe2x80x94A line of the flash memory""s cell.
An ONO layer 102 is formed on the substrate 100, and the bit lines 106 are formed thereon by an ion implanting process. In the same time, a bit diffusion oxide 108 is formed on the bit lines 106. Thereafter, a polysilicon layer, used as word line 104, is fabricated on the ONO layer 102 and the bit lines 106 to construct the flash memory array. The conventional flash memory""s cell 110 comprises a first bit line 106a and a second bit line 106b, and the charges are trapped near the sides of the two bit lines 106a, 106b. 
During a reading operation, the charges 112a near the first bit line 106a of ONO layer 102 are read in turn. Afterwards, the charges 112b near the second bit line 106b of ONO layer 102 are also read. The reading mode of the cell is bit line by bit line to acquire the data status, and the reading current only comes from a single path 114, such as channel 116, so that the reading current is severely minimized. If the reading current through each of channel is increased, the reading voltage imposed on the first bit line 106a and the second bit line 106b must also be increased such that the charges stored will be mostly lost.
Consequently, the reading current induced from the conventional flash memory mode is too small to enhance reading speed. Additionally, at the same reading speed corresponding to a higher reading voltage, the operation numbers decrease leading to a reduction in the flash memory""s life.
A problem encountered with the conventional flash memory is that the reading current thereof is extremely small so that the reading speed is decreased. Moreover, imposition of a higher reading voltage on the flash memory""s cell reduces the operation life thereof.
As a result, the primary object of the present invention is to utilize the flash memory with dual-channels to increase the reading current, thereby effectively increasing the reading speed of the flash memory.
Another object of the present invention is to use a lower reading voltage corresponding to an optimum reading current to prevent charges from running off, and to increase the operation rates of the flash memory.
According to the above objects, the present invention sets forth a method of operating a flash memory with symmetrical dual-channels. An ONO layer is formed on the substrate. Afterwards, bit line patterns are defined by lithography and etching processes, and then an ion implanting process is performed to form bit lines on the substrate according to the bit lines pattern. After that, the bit line diffusion oxide is formed on the bit lines. Finally, a polysilicon layer is formed on the ONO layer and the bit lines to generate the flash memory having unit cells with symmetrical dual-channels. Specifically, the operation modes of flash memory with symmetrical dual-channels essentially comprise writing and reading procedures.
During the writing procedure, a writing voltage is applied to the second bit line to program electrically the unit cell with symmetrical dual-channels and charges are retained in both sides of the second bit lines to indicate the data status. Thereafter, both a first bit line and a third bit line are grounded. Next, a positive voltage is imposed on the second word line. Finally, both a first word line and a third word line are grounded. A critical voltage is induced by these retained charges to complete a bit writing process.
During the reading procedure, a selective voltage is added to the first bit line and the third bit line to select the second bit line with symmetrical dual-channels. Then, the second bit line is grounded. After that, the reading voltage is exerted on the second bit line to fetch the reading current which is the sum of total current through the symmetrical dual-channels for increasing the reading speed of the flash memory.
In the present invention, the method for operating the non-volatile memory with symmetrical dual-channels is used to simultaneously output reading currents that enhance the reading speed of the data signals. Alternatively, a lower reading voltage corresponding to the optimum reading current increases the operation rates of the flash memory.